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| (R) EMIF10-LCD01C2 10 LINE EMI FILTER AND ESD PROTECTION IPADTM MAIN PRODUCT CHARACTERISTICS: Where EMI filtering in ESD sensitive equipment is required : LCD for Mobile phones Computers and printers Communication systems MCU Boards DESCRIPTION The EMIF10-LCD01C2 is a 10 line highly integrated devices designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interferences. The EMIF10 flip chip packaging means the package size is equal to the die size. This filter includes an ESD protection circuitry, which prevents the device from destruction when subjected to ESD surges up 15kV. BENEFITS Lead free coated Flip-Chip (25 bumps) Figure 1: Pin Configuration (bump side) 5 I5 I10 GND 4 I4 I9 GND 3 I3 I8 GND 2 I2 I7 GND 1 I1 I6 GND A B C D E EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consuming: < 7mm2 Coating resin on back side Very thin package: 0.69 mm High efficiency in ESD suppression on input pins (IEC61000-4-2 level 4) High reliability offered by monolithic integration High reducing of parasitic elements through integration and wafer level packaging. Lead free package O10 O5 O9 O4 O8 O3 O7 O2 O6 O1 Figure 2: Basic Cell Configuration Low-pass Filter Input Output Ri/o = 100 Cline = 35pF COMPLIES WITH THE FOLLOWING STANDARDS: IEC61000-4-2: Level 4 input pins 15kV (air discharge) 8kV (contact discharge) Level 1 output pins 2kV (air discharge) 2kV (contact discharge) MIL STD 833E - Method 3015-6 Class 3 GND GND GND Table 1: Order Code Part Number EMIF10-LCD01C2 August 2005 REV. 1 Marking FL 1/7 EMIF10-LCD01C2 Table 2: Absolute Maximum Ratings (Tamb = 25C) Symbol Tj Top Tstg Junction temperature Operating temperature range Storage temperature range Parameter Value 125 -40 to + 85 -55 to +150 Unit C C C Table 3: Electrical Characteristics (Tamb = 25C) Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Parameter Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic resistance Peak pulse current Series resistance between Input & Output Input capacitance per line Test conditions IR = 1 mA VRM = 3V 90 @ 0V bias Induced rise and fall time 10-90% at 26 MHz frequency signal V = 1.9 V (Rt / Ft input 1 ns, 50 impedance generator) 100 28 8 (1) Min. 6 Typ. 8 Max. 10 500 110 35 Unit V nA pF ns IPP VCL VBR VRM IRM IR VF V IF I Symbol VBR IRM RI/O Cline Rt / Ft (1) guaranteed by design Figure 3: S21(dB) all lines attenuation measurement and Aplac simulation Figure 4: Analog cross talk measurements 2/7 EMIF10-LCD01C2 Figure 5: ESD response to IEC61000-4-2 (+15kV air discharge) on one input and on one output Figure 6: ESD response to IEC61000-4-2 (-15kV air discharge) on one input and on one output Vin Vout Figure 7: Line capacitance versus applied voltage Figure 8: Rise time 10-90% measurements with 1.9V signal at 26 MHz frequency (50 generator) CLine(pF) 35 30 25 20 15 10 5 0 0.0 1.0 VLine(V) 2.0 3.0 4.0 5.0 Figure 9: Fall time 10-90% measurements with 1.9V signal at 26 MHz frequency (50 generator) 3/7 EMIF10-LCD01C2 Figure 10: Aplac model EMIF10-LCD01C1 model Ground return Figure 11: Aplac parameters ZRZ structure aplacvar Remif10low 100 aplacvar Cemif10flow 17.5pF Bumps aplacvar Lbump 50pH aplacvar Rbump 20m aplacvar Cbump 1.5pF Bulk aplacvar Rsub 100m Gnd connections aplacvar Rgnd 100m aplacvar Lgnd 200pH aplacvar Cgnd 0.15pF BV = 7 CJO = Cemif10low IBV = 1u IKF = 1000 IS = 10f ISR = 100p N=1 M = 0.3333 RS = 0.015 VJ = 0.6 TT = 50n Figure 12: Order Code EMIF EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package C = Flip-Chip x = 1: 500m, Bump = 315m = 2: Leadfree Pitch = 500m, Bump = 315m = 3: Leadfree Pitch = 400m, Bump = 250m yy - xxx zz Cx 4/7 EMIF10-LCD01C2 Figure 13: FLIP-CHIP Package Mechanical Data 500m 50 315m 50 695m 75 500m 50 2.64mm 50m 2.64mm 50m 250m 40 Figure 14: Foot Print Recommendations Figure 15: Marking Copper pad Diameter : 250m recommended , 300m max Dot, ST logo xx = marking z = packaging location yww = datecode (y = year ww = week) 545 400 545 Solder stencil opening : 330m E Solder mask opening recommendation : 340m min for 315m copper pad diameter xxz y ww 100 230 All dimensions in m 5/7 EMIF10-LCD01C2 Figure 16: FLIP-CHIP Tape and Reel Specification Dot identifying Pin A1 location 4 +/- 0.1 O 1.5 +/- 0.1 1.75 +/- 0.1 3.5 +/- 0.1 0.73 +/- 0.05 All dimensions in mm In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Part Number EMIF10-LCD01C2 Table 4: Ordering Information Note: Further packing information available in the application notes - AN1235: ''Flip-Chip: Package description and recommandations for use'' - AN1751: "EMI Filters: Recommendations and measurements" 8 +/- 0.3 STE STE STE xxz yww xxz yww xxz yww 4 +/- 0.1 User direction of unreeling Marking FL Package Flip-Chip Weight 9.3 mg Base qty 5000 Delivery mode Tape & reel (7") Table 5: Revision History Date 12-Aug-2005 Revision 1 First issue Description of Changes 6/7 EMIF10-LCD01C2 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 7/7 |
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